PLL synthesizers typically include a PFD which compares the input reference frequency to a sub-multiple of the output frequency (e.g., divided by N with a digital divider). The PFD generates up and down pulses which are applied to the charge pump. A conventional tri-state PFD includes a pair of bi-stable devices (e.g., D-type flip-flops) and gating logic. Because there is mismatch in the clock-to-Q delay in the flip-flops as well as mismatch in the reset-to-Q delay, the up and down pulses have slightly mismatched pulse widths which leads to output offset error. Moreover, any mismatch in the propagation delays of the gating logic in the up and down paths between the PFD and the charge pump will cause an output offset which results in static phase error.
The current sources of the single-ended charge pump of conventional dual bandwidth PLL synthesizers typically utilize different types of devices for the pump up and pump down current sources in the charge pump, e.g., a PMOS device for up current pulses and an NMOS device for down current. Typically, the matching between the currents from the two different devices is no better than five percent. The result is mismatched up and down current pulse magnitudes, that the charge pump generates. The PLL structure that is commonly used in conventional synthesizers is a closed loop feedback system with two integrators in the forward path. Hence the PLL synthesizer will reach equilibrium with whatever static phase error the PLL synthesizer needs between the PFD inputs to ensure DC balance at the loop filter node connected to the charge pump output. The DC or average value of the static phase error will be the amount required to cancel out the excess charge delivered to the loop filter due to the mismatch. For example, a mismatch of 5% with a 3 ns minimum PFD turn-on time would result in a phase skew of about 150 ps between the PFD inputs. In this example, if the RF output frequency is about 1850 MHz, a phase skew of 150 ps would corresponds to a static phase error of 100° at the output. Similarly, other imperfections in the PFD and/or the conventional single-ended charge pump, such as charge injection in the charge pump switches and leakage current at the output, will result in static phase error at the output of the PLL.
A prior art PLL circuit which attempts to reduce 1/f noise generated by the charge pump is disclosed in U.S. Pat. No. 6,111,470, incorporated herein by reference. The chopper stabilization technique as disclosed in the '470 patent will reduce the 1/f noise component but the single-ended design is still prone to static phase error. The PLL of the '470 patent employs a single-ended charge pump with only one output terminal which relies on a current mirror circuit to provide matching current up and current down pulses. However, the inherent current losses in the current mirror circuit, as well as the difference in propagation delay between the direct path to the output and the path through the current mirror to the output, results in a mismatch in the amplitude as well as timing between the actual up and down current pulses at the output. Also, since the elements being chopped are not identical (one device is a current source only and the other device is a current source and a current mirror), the relatively high mismatch error being chopped will result in a high spur level at the chopping rate. Moreover, static phase error resulting from the switch charge injection and output leakage will not be reduced using the chopping technique and design as disclosed in the '470 patent.
A conventional differential charge pump may be employed in a PLL to improve the matching of the current up and down pulses. A typical differential charge pump attempts to match current sources of the same type, e.g., PMOS to PMOS and NMOS to NMOS, rather than PMOS to NMOS as in the single-ended charge pump described above. A typical differential charge pump utilizes a pair of PMOS and NMOS devices to generate up current pulses and another pair of PMOS and NMOS devices to generate down current pulses. However, the PMOS and NMOS devices of a differential charge pump have a residual mismatch due to process variations. Leakage, headroom, and die area set a limit on how much these variations can be reduced. Hence, conventional differential charge pumps employed in a PLL do not provide completely matched current up and current down pulses needed to eliminate static phase offset.